Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126399" target="_blank" >RIV/00216305:26230/17:PU126399 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11377/" target="_blank" >https://www.fit.vut.cz/research/publication/11377/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3067695.3084212" target="_blank" >10.1145/3067695.3084212</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming

Popis výsledku v původním jazyce

The aim of the paper is to introduce a new parallel approach to evolutionary optimization of digital circuits described on transistor level. The evolutionary optimization is guided by the fitness function employing a simulator of candidate circuits. A new discrete simulator was introduced to achieve a good trade-off between precision and cost of circuit evaluations. The simulator is based on event-driven simulation. Precise numeric SPICE simulator is regularly called to validate simulation results. To increase the speed of evolution, three parallel approaches were proposed: (i) thread level parallelism, (ii) multiple computing nodes which collectively communicate and distribute the best solution, and (iii) client-server architecture eliminating a limited count of SPICE simulator instances.

Název v anglickém jazyce

Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming

Popis výsledku anglicky

The aim of the paper is to introduce a new parallel approach to evolutionary optimization of digital circuits described on transistor level. The evolutionary optimization is guided by the fitness function employing a simulator of candidate circuits. A new discrete simulator was introduced to achieve a good trade-off between precision and cost of circuit evaluations. The simulator is based on event-driven simulation. Precise numeric SPICE simulator is regularly called to validate simulation results. To increase the speed of evolution, three parallel approaches were proposed: (i) thread level parallelism, (ii) multiple computing nodes which collectively communicate and distribute the best solution, and (iii) client-server architecture eliminating a limited count of SPICE simulator instances.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference

ISBN

978-1-4503-4939-0

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

1849-1856

Název nakladatele

Association for Computing Machinery

Místo vydání

Berlin

Místo konání akce

Berlin

Datum konání akce

15. 7. 2017

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000625865500312