Packet Classification with Limited Memory Resources

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126458" target="_blank" >RIV/00216305:26230/17:PU126458 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD.2017.61" target="_blank" >http://dx.doi.org/10.1109/DSD.2017.61</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2017.61" target="_blank" >10.1109/DSD.2017.61</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Packet Classification with Limited Memory Resources

Popis výsledku v původním jazyce

Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.

Název v anglickém jazyce

Packet Classification with Limited Memory Resources

Popis výsledku anglicky

Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/VI20152019001" target="_blank" >VI20152019001: Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

In proceedings 2017 Euromicro Conference on Digital System Design

ISBN

978-1-5386-2145-5

ISSN

—

e-ISSN

—

Počet stran výsledku

5

Strana od-do

179-183

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Vieden

Místo konání akce

Vídeň

Datum konání akce

30. 8. 2017

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000427097100024