Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU131689" target="_blank" >RIV/00216305:26230/19:PU131689 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11870/" target="_blank" >https://www.fit.vut.cz/research/publication/11870/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/LATW.2019.8704593" target="_blank" >10.1109/LATW.2019.8704593</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

Popis výsledku v původním jazyce

As electronic systems penetrate into areas in which reliable computing is required, new methods incorporating reliability into these systems arise. It is important to properly test and evaluate parameters of such methods before the actual implementation and the practical usage in an application. Generally, in our research, we are focusing on the acceleration of reliable design through creation of automation methods. However, for this purpose, it is important to develop tools to automatically analyze reliability properties of the system after the method is applied. In our previous work, we developed the Fault Tolerance ESTimation (FT-EST) framework, which specializes on minimizing the requirement for user intervention. In this paper, we are using the framework to collect the data, however, the research presented in this paper primarily focuses on the possibility to automatically analyze such data. Our previous papers were focused on particular methods of the automatic reliability insertion and evaluation while this paper introduces new reliability indicators based on low-level properties of FPGA configuration bitstreams. Currently, we are limiting our research to SRAM-based FPGA systems and focus on the VHDL and C++ (in the combination with High-level Synthesis) languages.

Název v anglickém jazyce

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

Popis výsledku anglicky

As electronic systems penetrate into areas in which reliable computing is required, new methods incorporating reliability into these systems arise. It is important to properly test and evaluate parameters of such methods before the actual implementation and the practical usage in an application. Generally, in our research, we are focusing on the acceleration of reliable design through creation of automation methods. However, for this purpose, it is important to develop tools to automatically analyze reliability properties of the system after the method is applied. In our previous work, we developed the Fault Tolerance ESTimation (FT-EST) framework, which specializes on minimizing the requirement for user intervention. In this paper, we are using the framework to collect the data, however, the research presented in this paper primarily focuses on the possibility to automatically analyze such data. Our previous papers were focused on particular methods of the automatic reliability insertion and evaluation while this paper introduces new reliability indicators based on low-level properties of FPGA configuration bitstreams. Currently, we are limiting our research to SRAM-based FPGA systems and focus on the VHDL and C++ (in the combination with High-level Synthesis) languages.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

20th IEEE Latin American Test Symposium (LATS 2019)

ISBN

978-1-7281-1756-0

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

93-96

Název nakladatele

IEEE Computer Society

Místo vydání

Santiago

Místo konání akce

Hotel Fundador, Santiago de Chile

Datum konání akce

11. 3. 2019

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000469850000022