Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126442" target="_blank" >RIV/00216305:26230/17:PU126442 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11493/" target="_blank" >https://www.fit.vut.cz/research/publication/11493/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EWDTS.2017.8110127" target="_blank" >10.1109/EWDTS.2017.8110127</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation

Popis výsledku v původním jazyce

Some environments (e.g. space, aerospace or medical systems) require electronic systems to withstand an increased occurrence of faults. Moreover, the failure of these electronic systems can cause high economical losses or endanger human health. Fault tolerance is one of the techniques, the goal of which is to avoid such situations. This paper presents an approach to evaluate the degree of importance of individual system partitions when High-Level Synthesis (HLS) methodology is used. The importance of individual partitions was evaluated by the usage of our approach to fault-tolerant data-paths design which is based on the HLS input specification modification. The partitions are formed by sets of variables and operations. A brief description of the approach to fault tolerance in HLS is shown in the paper as well. Our experiments are evaluated using an SRAM-based FPGA evaluation platform which allows us to analyze fault tolerance properties of the Design Under Test (DUT). In the evaluation platform, functional verification in combination with fault injection is utilized.

Název v anglickém jazyce

Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation

Popis výsledku anglicky

Some environments (e.g. space, aerospace or medical systems) require electronic systems to withstand an increased occurrence of faults. Moreover, the failure of these electronic systems can cause high economical losses or endanger human health. Fault tolerance is one of the techniques, the goal of which is to avoid such situations. This paper presents an approach to evaluate the degree of importance of individual system partitions when High-Level Synthesis (HLS) methodology is used. The importance of individual partitions was evaluated by the usage of our approach to fault-tolerant data-paths design which is based on the HLS input specification modification. The partitions are formed by sets of variables and operations. A brief description of the approach to fault tolerance in HLS is shown in the paper as well. Our experiments are evaluated using an SRAM-based FPGA evaluation platform which allows us to analyze fault tolerance properties of the Design Under Test (DUT). In the evaluation platform, functional verification in combination with fault injection is utilized.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE East-West Design & Test Symposium

ISBN

978-1-5386-3299-4

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

359-364

Název nakladatele

IEEE Computer Society

Místo vydání

Novi Sad

Místo konání akce

Dr Zorana Đinđića 1, 21101, Novi Sad

Datum konání akce

29. 9. 2017

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000426878200100