EA-based refactoring of mapped logic circuits
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132968" target="_blank" >RIV/00216305:26230/19:PU132968 - isvavai.cz</a>
Výsledek na webu
<a href="https://www.fit.vut.cz/research/publication/11847/" target="_blank" >https://www.fit.vut.cz/research/publication/11847/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISCAS.2019.8702084" target="_blank" >10.1109/ISCAS.2019.8702084</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
EA-based refactoring of mapped logic circuits
Popis výsledku v původním jazyce
The increasing complexity of the designs and prob-lematic scalability of original representations led to a shift ininternal representations used in logic synthesis and optimization. Heterogeneous representations were replaced with homogeneous intermediate representations. And-inverter graph (AIG) has been identified as the most promising structure for scalable logic optimization and many efficient algorithms were implemented on top of it. However, the inability of AIG to efficiently represent XOR gates together with heuristic nature of logic optimization algorithms leads to some inefficiency causing that the logic can be further minimized even after it has been mapped. This paper presents an optimization technique based on refactoring targeting mapped combinational circuits. It iteratively selects large cones of logic, optimizes them and returns them back to the original structure provided that there is an improvement in some metric.Performance of the method is evaluated on a set of complex academic and industrial benchmarks. We show that a 9.2%reduction in area can be achieved in average compared to thehighly optimized results obtained using the academic state-of-the-art synthesis tool. In average, more than 14% reduction was observed for arithmetic circuits.
Název v anglickém jazyce
EA-based refactoring of mapped logic circuits
Popis výsledku anglicky
The increasing complexity of the designs and prob-lematic scalability of original representations led to a shift ininternal representations used in logic synthesis and optimization. Heterogeneous representations were replaced with homogeneous intermediate representations. And-inverter graph (AIG) has been identified as the most promising structure for scalable logic optimization and many efficient algorithms were implemented on top of it. However, the inability of AIG to efficiently represent XOR gates together with heuristic nature of logic optimization algorithms leads to some inefficiency causing that the logic can be further minimized even after it has been mapped. This paper presents an optimization technique based on refactoring targeting mapped combinational circuits. It iteratively selects large cones of logic, optimizes them and returns them back to the original structure provided that there is an improvement in some metric.Performance of the method is evaluated on a set of complex academic and industrial benchmarks. We show that a 9.2%reduction in area can be achieved in average compared to thehighly optimized results obtained using the academic state-of-the-art synthesis tool. In average, more than 14% reduction was observed for arithmetic circuits.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Návaznosti výsledku
Projekt
Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Ostatní
Rok uplatnění
2019
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
ISBN
978-1-7281-0397-6
ISSN
—
e-ISSN
—
Počet stran výsledku
5
Strana od-do
1-5
Název nakladatele
IEEE Computer Society Press
Místo vydání
Red Hook, NY
Místo konání akce
Sapporo
Datum konání akce
26. 5. 2019
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
000483076400021