The State-of-the-Art of the Logic representations for the synthesis
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00308450" target="_blank" >RIV/68407700:21240/17:00308450 - isvavai.cz</a>
Výsledek na webu
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DOI - Digital Object Identifier
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Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
The State-of-the-Art of the Logic representations for the synthesis
Popis výsledku v původním jazyce
This report summarizes the State-of-the-Art in the logic synthesis representations. The representation by Sum of Products (SOPs) was used in first synthesis EDA tools. Later, a representation based on binary decision tree, BDD, has been introduced. However, these representations were not scallable. To address scalability AIGs were implemented in academic synthesis tool ABC, which seemed to be an ultimate solution to the synthesis. However circuits for which ABC synthesis is weak have been found. New representation based on AIG and BDD, namely MIGs, XMGs and BBDDs were created as an attempt to help synthesis process to optimize networks efficiently.
Název v anglickém jazyce
The State-of-the-Art of the Logic representations for the synthesis
Popis výsledku anglicky
This report summarizes the State-of-the-Art in the logic synthesis representations. The representation by Sum of Products (SOPs) was used in first synthesis EDA tools. Later, a representation based on binary decision tree, BDD, has been introduced. However, these representations were not scallable. To address scalability AIGs were implemented in academic synthesis tool ABC, which seemed to be an ultimate solution to the synthesis. However circuits for which ABC synthesis is weak have been found. New representation based on AIG and BDD, namely MIGs, XMGs and BBDDs were created as an attempt to help synthesis process to optimize networks efficiently.
Klasifikace
Druh
O - Ostatní výsledky
CEP obor
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OECD FORD obor
20206 - Computer hardware and architecture
Návaznosti výsledku
Projekt
<a href="/cs/project/GA16-05179S" target="_blank" >GA16-05179S: Výzkum vztahů a společných vlastností spolehlivých a bezpečných architektur založených na programovatelných obvodech</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Ostatní
Rok uplatnění
2017
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů