Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00318374" target="_blank" >RIV/68407700:21240/18:00318374 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1016/j.microrel.2017.12.031" target="_blank" >https://doi.org/10.1016/j.microrel.2017.12.031</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.microrel.2017.12.031" target="_blank" >10.1016/j.microrel.2017.12.031</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR

Popis výsledku v původním jazyce

Although contemporary logic synthesis performs well on random logic, it may produce subpar results in XOR-intensive circuits. This indicated the need of equal status of XORs and ANDs, with their respective Negation-Permutation-Negation (NPN) equivalents in logic synthesis procedures. To test the hypothesis of XOR importance, we introduced a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graph (XAIG). As the first test, we implemented a rewriting algorithm in the logic synthesis and optimization package ABC and compared it with the standard rewriting algorithm based on the AND-Inverter Graph (AIG). The main experimental evaluation was performed in the context of a complete logic synthesis process, particularly the FPGA LUT mapping and mapping to standard cells. To eliminate algorithmic noise, input circuit descriptions were randomly modified while preserving their semantics. In the FPGA mapping, the XAIG rewriting dominated the AIG procedure in 8.6% of cases, while it was dominated in 1.6% of cases. For the standard cells mapping, the respective percentages were 3% and 1.5%. We conclude that the best rewriting is a combination of both approaches.

Název v anglickém jazyce

Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR

Popis výsledku anglicky

Although contemporary logic synthesis performs well on random logic, it may produce subpar results in XOR-intensive circuits. This indicated the need of equal status of XORs and ANDs, with their respective Negation-Permutation-Negation (NPN) equivalents in logic synthesis procedures. To test the hypothesis of XOR importance, we introduced a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graph (XAIG). As the first test, we implemented a rewriting algorithm in the logic synthesis and optimization package ABC and compared it with the standard rewriting algorithm based on the AND-Inverter Graph (AIG). The main experimental evaluation was performed in the context of a complete logic synthesis process, particularly the FPGA LUT mapping and mapping to standard cells. To eliminate algorithmic noise, input circuit descriptions were randomly modified while preserving their semantics. In the FPGA mapping, the XAIG rewriting dominated the AIG procedure in 8.6% of cases, while it was dominated in 1.6% of cases. For the standard cells mapping, the respective percentages were 3% and 1.5%. We conclude that the best rewriting is a combination of both approaches.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/GA16-05179S" target="_blank" >GA16-05179S: Výzkum vztahů a společných vlastností spolehlivých a bezpečných architektur založených na programovatelných obvodech</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microelectronics Reliability

ISSN

0026-2714

e-ISSN

—

Svazek periodika

81

Číslo periodika v rámci svazku

Feb.

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

13

Strana od-do

274-286

Kód UT WoS článku

000425576300032

EID výsledku v databázi Scopus

2-s2.0-85041479835