PoLibSi: Path Towards Intrinsically Reconfigurable Components

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU134148" target="_blank" >RIV/00216305:26230/19:PU134148 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD.2019.00055" target="_blank" >http://dx.doi.org/10.1109/DSD.2019.00055</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2019.00055" target="_blank" >10.1109/DSD.2019.00055</a>

Jazyk výsledku

angličtina

Název v původním jazyce

PoLibSi: Path Towards Intrinsically Reconfigurable Components

Popis výsledku v původním jazyce

One of the main research directions of polymorphic electronics is focused on various issues connected with the design of basic polymorphic components - polymorphic gates. Without a sufficient amount of polymorphic gates offering good properties, conventional electronics will be most likely the preferred way before polymorphic electronics in application scenarios targeting multifunctional behaviour or reconfiguration. The main objective of this paper is to propose a library called PoLibSi which contains eight sets of efficient bi-functional two-input polymorphic gates, whose function is selected by mutual polarity of dedicated power rails. The gate sets differ in the transistor type (conventional MOSFET, emerging double-gate ambipolar transistors), feature the gate sets were optimized to (transistor count, delay, power consumption) and input impedance constraint. The individual gates were designed by means of using an evolutionary based approach and further validated by HSPICE simulations. Each gate implementation includes a schematic, HSPICE description and simulation results. Moreover, propagation delay and power consumption is provided for all MOSFET based gates. Furthermore, each gate set is complete - it provides efficient implementation of any pair of two-input Boolean functions. Besides providing polymorphic gates with better properties to the research society, the aim of the proposed library is to improve the synthesis of polymorphic circuits in terms of the resulting size, as it is also shown in the paper. Finally, the PoLibSi library is available at: www.fit.vutbr.cz/~inevoral/polibsi

Název v anglickém jazyce

PoLibSi: Path Towards Intrinsically Reconfigurable Components

Popis výsledku anglicky

One of the main research directions of polymorphic electronics is focused on various issues connected with the design of basic polymorphic components - polymorphic gates. Without a sufficient amount of polymorphic gates offering good properties, conventional electronics will be most likely the preferred way before polymorphic electronics in application scenarios targeting multifunctional behaviour or reconfiguration. The main objective of this paper is to propose a library called PoLibSi which contains eight sets of efficient bi-functional two-input polymorphic gates, whose function is selected by mutual polarity of dedicated power rails. The gate sets differ in the transistor type (conventional MOSFET, emerging double-gate ambipolar transistors), feature the gate sets were optimized to (transistor count, delay, power consumption) and input impedance constraint. The individual gates were designed by means of using an evolutionary based approach and further validated by HSPICE simulations. Each gate implementation includes a schematic, HSPICE description and simulation results. Moreover, propagation delay and power consumption is provided for all MOSFET based gates. Furthermore, each gate set is complete - it provides efficient implementation of any pair of two-input Boolean functions. Besides providing polymorphic gates with better properties to the research society, the aim of the proposed library is to improve the synthesis of polymorphic circuits in terms of the resulting size, as it is also shown in the paper. Finally, the PoLibSi library is available at: www.fit.vutbr.cz/~inevoral/polibsi

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2019 22nd Euromicro Conference on Digital System Design (DSD)

ISBN

978-1-7281-2861-0

ISSN

—

e-ISSN

—

Počet stran výsledku

7

Strana od-do

328-334

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Kallithea, Chalkidiki

Místo konání akce

Athos Palace Hotel, Solinas, Kallithea 63077, Ch

Datum konání akce

28. 8. 2019

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000722275400046