CMOS Gates with Second Function

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130700" target="_blank" >RIV/00216305:26230/18:PU130700 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ISVLSI.2018.00025" target="_blank" >http://dx.doi.org/10.1109/ISVLSI.2018.00025</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISVLSI.2018.00025" target="_blank" >10.1109/ISVLSI.2018.00025</a>

Jazyk výsledku

angličtina

Název v původním jazyce

CMOS Gates with Second Function

Popis výsledku v původním jazyce

In this paper, a new approach to design of multifunctional digital circuits is presented. It is based on adoption of polymorphic electronics paradigm which permits digital circuits to exhibit more than one function while preserving the same structure. In that case only components of the circuit (gates) have to be multifunctional. Individual gates have typically built-in sensitivity to the occurrence of some phenomena invoking the function change (e.g. power supply level etc.), which means that no dedicated net is required for that purpose. One of the key advantages of such circuits is the efficiency in terms of size. In this paper, MOS transistors are exploited in an unconventional manner where the circuit function selection depends just on the condition of power supply voltage rails, which is otherwise typical for polymorphic circuits utilizing ambipolar transistors. Furthermore, a first complete set of successfully simulated two-input polymorphic gates was obtained. These gates show the best parameters of all the previously published polymorphic gates - high input impedance and low output impedance, short time of signal propagation, low power consumption and low transistor count being used. Wide range of proposed polymorphic gates (function combinations) may help to obtain more efficient results during synthesis.

Název v anglickém jazyce

CMOS Gates with Second Function

Popis výsledku anglicky

In this paper, a new approach to design of multifunctional digital circuits is presented. It is based on adoption of polymorphic electronics paradigm which permits digital circuits to exhibit more than one function while preserving the same structure. In that case only components of the circuit (gates) have to be multifunctional. Individual gates have typically built-in sensitivity to the occurrence of some phenomena invoking the function change (e.g. power supply level etc.), which means that no dedicated net is required for that purpose. One of the key advantages of such circuits is the efficiency in terms of size. In this paper, MOS transistors are exploited in an unconventional manner where the circuit function selection depends just on the condition of power supply voltage rails, which is otherwise typical for polymorphic circuits utilizing ambipolar transistors. Furthermore, a first complete set of successfully simulated two-input polymorphic gates was obtained. These gates show the best parameters of all the previously published polymorphic gates - high input impedance and low output impedance, short time of signal propagation, low power consumption and low transistor count being used. Wide range of proposed polymorphic gates (function combinations) may help to obtain more efficient results during synthesis.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

ISBN

978-1-5386-7099-6

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

82-87

Název nakladatele

IEEE Computer Society

Místo vydání

Hong Kong

Místo konání akce

The Hong Kong Polytechnic University, 11 Yuk Cho

Datum konání akce

9. 7. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000443443500015