Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU142901" target="_blank" >RIV/00216305:26230/21:PU142901 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12488/" target="_blank" >https://www.fit.vut.cz/research/publication/12488/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD53832.2021.00088" target="_blank" >10.1109/DSD53832.2021.00088</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs

Popis výsledku v původním jazyce

This paper presents and evaluates the possibility of automatic design of fault-tolerant systems from unhardened systems. We present an overview of our toolkit with its three main components: 1) fault-tolerant structures insertion (which we call helpers); 2) fault-tolerant structures selection (called guiders); and 3) automatic testbed generation, incorporating advanced acceleration techniques to accelerate the test and evaluation. Our approach is targeting complete independence on the HW description language and its abstraction level, however, for our case study, we focus on VHDL in combination with fine-grained n-modular redundancy. In the case study part of this paper, we proved that it is undoubtedly beneficial to select a proper fault tolerance method for each partition separately. Three experimental systems were developed with the usage of our method. Two of them achieved better reliability parameter while even lowering their chip area, compared to static allocation of equivalent fault tolerance technique type. In the case study, we target the best median time to failure, the so-called t50, however, our method is not dependent on this parameter and arbitrary optimization target can be selected, as soon as it is measurable.

Název v anglickém jazyce

Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs

Popis výsledku anglicky

This paper presents and evaluates the possibility of automatic design of fault-tolerant systems from unhardened systems. We present an overview of our toolkit with its three main components: 1) fault-tolerant structures insertion (which we call helpers); 2) fault-tolerant structures selection (called guiders); and 3) automatic testbed generation, incorporating advanced acceleration techniques to accelerate the test and evaluation. Our approach is targeting complete independence on the HW description language and its abstraction level, however, for our case study, we focus on VHDL in combination with fine-grained n-modular redundancy. In the case study part of this paper, we proved that it is undoubtedly beneficial to select a proper fault tolerance method for each partition separately. Three experimental systems were developed with the usage of our method. Two of them achieved better reliability parameter while even lowering their chip area, compared to static allocation of equivalent fault tolerance technique type. In the case study, we target the best median time to failure, the so-called t50, however, our method is not dependent on this parameter and arbitrary optimization target can be selected, as soon as it is measurable.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/8A18014" target="_blank" >8A18014: Cyber Security for Cross Domain Reliable Dependable Automated Systems</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021

ISBN

978-1-6654-2703-6

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

549-552

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Palermo

Místo konání akce

Palermo

Datum konání akce

1. 9. 2021

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000728394500079