Optimization of BDD-based Approximation Error Metrics Calculations

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU144471" target="_blank" >RIV/00216305:26230/22:PU144471 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00028" target="_blank" >http://dx.doi.org/10.1109/ISVLSI54635.2022.00028</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00028" target="_blank" >10.1109/ISVLSI54635.2022.00028</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Optimization of BDD-based Approximation Error Metrics Calculations

Popis výsledku v původním jazyce

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.

Název v anglickém jazyce

Optimization of BDD-based Approximation Error Metrics Calculations

Popis výsledku anglicky

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GJ20-02328Y" target="_blank" >GJ20-02328Y: CAQtuS: Počítačem podporovaná kvantitativní syntéza</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)

ISBN

978-1-6654-6605-9

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

86-91

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Paphos

Místo konání akce

Kypr

Datum konání akce

4. 7. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000886230500015