Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F24%3APU151217" target="_blank" >RIV/00216305:26230/24:PU151217 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.23919/DATE58400.2024.10546795" target="_blank" >http://dx.doi.org/10.23919/DATE58400.2024.10546795</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.23919/DATE58400.2024.10546795" target="_blank" >10.23919/DATE58400.2024.10546795</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Popis výsledku v původním jazyce

A fundamental assumption for search-based circuit approximation methods is the ability to massively and efficiently traverse the search space and evaluate candidate solutions. For complex approximate circuits (adders and multipliers), common error metrics, and error analysis approaches (SAT solving, BDD analysis), we perform a detailed analysis to understand the behavior of the error analysis methods under constrained resources, such as limited execution time. In addition, we show that when evaluating the error of a candidate approximate circuit, it is highly beneficial to reuse knowledge obtained during the evaluation of previous circuit instances to reduce the total design time. When an adaptive search strategy that drives the search towards promptly verifiable approximate circuits is employed, the method can discover circuits that exhibit better trade-offs between error and desired parameters (such as area) than the same method with unconstrained verification resources and within the same overall time budget. For 16-bit and 20-bit approximate multipliers, it was possible to achieve a 75% reduction in area when compared with the baseline method.

Název v anglickém jazyce

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Popis výsledku anglicky

A fundamental assumption for search-based circuit approximation methods is the ability to massively and efficiently traverse the search space and evaluate candidate solutions. For complex approximate circuits (adders and multipliers), common error metrics, and error analysis approaches (SAT solving, BDD analysis), we perform a detailed analysis to understand the behavior of the error analysis methods under constrained resources, such as limited execution time. In addition, we show that when evaluating the error of a candidate approximate circuit, it is highly beneficial to reuse knowledge obtained during the evaluation of previous circuit instances to reduce the total design time. When an adaptive search strategy that drives the search towards promptly verifiable approximate circuits is employed, the method can discover circuits that exhibit better trade-offs between error and desired parameters (such as area) than the same method with unconstrained verification resources and within the same overall time budget. For 16-bit and 20-bit approximate multipliers, it was possible to achieve a 75% reduction in area when compared with the baseline method.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GA24-10990S" target="_blank" >GA24-10990S: Strojové učení zohledňující hardware: Od automatizovaného návrhu k inovativním a vysvětlitelným řešením</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)

ISBN

979-8-3503-4859-0

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

1-6

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Valencia

Místo konání akce

Valencia

Datum konání akce

25. 3. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001253778900280