Technology Mapping for PAIG Optimized Polymorphic Circuits
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU147111" target="_blank" >RIV/00216305:26230/22:PU147111 - isvavai.cz</a>
Výsledek na webu
<a href="http://dx.doi.org/10.1109/DSD57027.2022.00112" target="_blank" >http://dx.doi.org/10.1109/DSD57027.2022.00112</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD57027.2022.00112" target="_blank" >10.1109/DSD57027.2022.00112</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Technology Mapping for PAIG Optimized Polymorphic Circuits
Popis výsledku v původním jazyce
The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit, whereas the currently selected function depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology. As a result of that, the perspective of their utilization for real applications becomes rather bleak. In recent years, several complete libraries of CMOS-compatible polymorphic gates were proposed. Synthesis of polymorphic circuits achieves a higher degree of complexity in comparison to the synthesis of an ordinary digital circuit. In past, many of yet proposed polymorphic circuits have been synthesized using evolutionary principles (EA, CGP, etc.). Research done in recent years indicates that the problem of scalable synthesis technique for the synthesis of complex polymorphic circuits could be solved by multi-level synthesis techniques such as And-Inverter-Graphs. The PAIG (Polymorphic And-Inverter-Graphs) concept and synthesis techniques based on it seems to be viable approach. This paper shows a how modern polymorphic gates could be used to obtain effective implementation of a real polymorphic circuit, synthesized by a PAIG based tool.
Název v anglickém jazyce
Technology Mapping for PAIG Optimized Polymorphic Circuits
Popis výsledku anglicky
The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit, whereas the currently selected function depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology. As a result of that, the perspective of their utilization for real applications becomes rather bleak. In recent years, several complete libraries of CMOS-compatible polymorphic gates were proposed. Synthesis of polymorphic circuits achieves a higher degree of complexity in comparison to the synthesis of an ordinary digital circuit. In past, many of yet proposed polymorphic circuits have been synthesized using evolutionary principles (EA, CGP, etc.). Research done in recent years indicates that the problem of scalable synthesis technique for the synthesis of complex polymorphic circuits could be solved by multi-level synthesis techniques such as And-Inverter-Graphs. The PAIG (Polymorphic And-Inverter-Graphs) concept and synthesis techniques based on it seems to be viable approach. This paper shows a how modern polymorphic gates could be used to obtain effective implementation of a real polymorphic circuit, synthesized by a PAIG based tool.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
20206 - Computer hardware and architecture
Návaznosti výsledku
Projekt
—
Návaznosti
S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2022
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22)
ISBN
978-1-6654-7404-7
ISSN
—
e-ISSN
—
Počet stran výsledku
8
Strana od-do
801-808
Název nakladatele
IEEE Computer Society
Místo vydání
Gran Canaria
Místo konání akce
Maspalomas, Gran Canaria, Spain
Datum konání akce
31. 8. 2022
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
—