Automated Synthesis of Commutative Approximate Arithmetic Operators

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F24%3APU152033" target="_blank" >RIV/00216305:26230/24:PU152033 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/CEC60901.2024.10612202" target="_blank" >http://dx.doi.org/10.1109/CEC60901.2024.10612202</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/CEC60901.2024.10612202" target="_blank" >10.1109/CEC60901.2024.10612202</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Automated Synthesis of Commutative Approximate Arithmetic Operators

Popis výsledku v původním jazyce

Approximate computing, leveraging the inherent resilience to errors, emerges as a promising strategy for reducing power consumption in digital systems. The primary objective of this paper is to introduce an efficient method based on Cartesian Genetic Programming for designing approximate arithmetic circuits with commutative property. Specifically, this work focuses on the design of 8-bit approximate multipliers and 32-bit approximate adders, both serving as foundational components for hardware accelerators in neural networks. We have identified that while the design of commutative approximate adders poses no issues for evolution, the design of commutative approximate multipliers represents a challenging problem causing the commonly used CGP stuck at highly sub-optimal solutions. In response to this challenge, we propose a novel application-specific mutation operator. This operator significantly enhances the efficiency of the search process, enabling the discovery of solutions that were previously unreachable. The achieved results revealed that imposing the requirement for a commutative property does not substantially compromise the quality-error trade-offs of the obtained approximate circuits, making the resulting Pareto front comparable to that of unconstrained designs.

Název v anglickém jazyce

Automated Synthesis of Commutative Approximate Arithmetic Operators

Popis výsledku anglicky

Approximate computing, leveraging the inherent resilience to errors, emerges as a promising strategy for reducing power consumption in digital systems. The primary objective of this paper is to introduce an efficient method based on Cartesian Genetic Programming for designing approximate arithmetic circuits with commutative property. Specifically, this work focuses on the design of 8-bit approximate multipliers and 32-bit approximate adders, both serving as foundational components for hardware accelerators in neural networks. We have identified that while the design of commutative approximate adders poses no issues for evolution, the design of commutative approximate multipliers represents a challenging problem causing the commonly used CGP stuck at highly sub-optimal solutions. In response to this challenge, we propose a novel application-specific mutation operator. This operator significantly enhances the efficiency of the search process, enabling the discovery of solutions that were previously unreachable. The achieved results revealed that imposing the requirement for a commutative property does not substantially compromise the quality-error trade-offs of the obtained approximate circuits, making the resulting Pareto front comparable to that of unconstrained designs.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GA22-02067S" target="_blank" >GA22-02067S: AppNeCo: Aproximativní neurovýpočty</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2024 IEEE Congress on Evolutionary Computation, CEC 2024 - Proceedings

ISBN

979-8-3503-0836-5

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

1-8

Název nakladatele

IEEE Computer Society

Místo vydání

Yokohama

Místo konání akce

Yokohama

Datum konání akce

30. 6. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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