Leveraging Design Static Analysis for Vertical Reuse in Functional Verification

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F26%3A0193872" target="_blank" >RIV/00216305:26230/26:0193872 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/11272820" target="_blank" >https://ieeexplore.ieee.org/document/11272820</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD67783.2025.00068" target="_blank" >10.1109/DSD67783.2025.00068</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Leveraging Design Static Analysis for Vertical Reuse in Functional Verification

Popis výsledku v původním jazyce

The Portable Test and Stimulus Standard (PSS) enables higher abstraction for simulation-based verification through graph-based stimulus generation, promoting modular reuse. However, achieving vertical reuse-integrating block-level PSS models into top-level ones-remains a significant challenge due to the manual effort required. This paper introduces static analysis as a critical phase in automating vertical reuse. Static analysis techniques, including data and control flow analyses combined with Satisfiability Modulo Theories solver for conditions resolving, are applied to trace signal paths from the top-level design to its submodules. Experimental validation demonstrates the applicability of the static analysis approach to the execution stage of a RISC-V processor and its scalability and efficiency using a configurable benchmark design with varying design sizes and hierarchical levels. The findings suggest that the static analysis provides enough information about interconnections and dependencies in the top-level design to determine connections necessary for automating the vertical reuse of PSS models.

Název v anglickém jazyce

Leveraging Design Static Analysis for Vertical Reuse in Functional Verification

Popis výsledku anglicky

The Portable Test and Stimulus Standard (PSS) enables higher abstraction for simulation-based verification through graph-based stimulus generation, promoting modular reuse. However, achieving vertical reuse-integrating block-level PSS models into top-level ones-remains a significant challenge due to the manual effort required. This paper introduces static analysis as a critical phase in automating vertical reuse. Static analysis techniques, including data and control flow analyses combined with Satisfiability Modulo Theories solver for conditions resolving, are applied to trace signal paths from the top-level design to its submodules. Experimental validation demonstrates the applicability of the static analysis approach to the execution stage of a RISC-V processor and its scalability and efficiency using a configurable benchmark design with varying design sizes and hierarchical levels. The findings suggest that the static analysis provides enough information about interconnections and dependencies in the top-level design to determine connections necessary for automating the vertical reuse of PSS models.

Druh

O - Ostatní výsledky

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů