Inference Energy Analysis in Context of Hardware-Aware NAS

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F26%3A0196475" target="_blank" >RIV/00216305:26230/26:0196475 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DDECS63720.2025.11006674" target="_blank" >http://dx.doi.org/10.1109/DDECS63720.2025.11006674</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS63720.2025.11006674" target="_blank" >10.1109/DDECS63720.2025.11006674</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Inference Energy Analysis in Context of Hardware-Aware NAS

Popis výsledku v původním jazyce

Hardware-aware neural architecture search (HW-aware NAS) methods are crucial for designing and optimizing deep neural networks (DNNs) for efficient deployment on hardware accelerators. In this work, we analyze two HW-aware NAS methods, EvoApproxNAS and ApproxDARTS, and investigate the impact of precise hardware parameters (such as energy) measurement using Timeloop on their performance. In particular, we compare this precise measurement approach with the original approach employed by EvoApproxNAS and ApproxDARTS, which relied on a simple analytical energy estimation based on the number of multiplications performed during the inference phase of the convolutional neural network (CNN). Our analysis demonstrates how the improved energy measurements enhance the search process of HW-aware NAS methods, resulting in more energy-efficient architectures. Furthermore, we highlight the importance of precise hardware parameters measurement, showing that accurate hardware modeling is critical for obtaining CNNs with good accuracy-energy trade-offs. Our results show, that without precise hardware parameter measurement, the HW-aware NAS can produce acceptable results but may fail to fully exploit the potential of hardware accelerator, especially if the 8xN-bit approximate multipliers are considered, ultimately limiting the efficiency of designed architectures.

Název v anglickém jazyce

Inference Energy Analysis in Context of Hardware-Aware NAS

Popis výsledku anglicky

Hardware-aware neural architecture search (HW-aware NAS) methods are crucial for designing and optimizing deep neural networks (DNNs) for efficient deployment on hardware accelerators. In this work, we analyze two HW-aware NAS methods, EvoApproxNAS and ApproxDARTS, and investigate the impact of precise hardware parameters (such as energy) measurement using Timeloop on their performance. In particular, we compare this precise measurement approach with the original approach employed by EvoApproxNAS and ApproxDARTS, which relied on a simple analytical energy estimation based on the number of multiplications performed during the inference phase of the convolutional neural network (CNN). Our analysis demonstrates how the improved energy measurements enhance the search process of HW-aware NAS methods, resulting in more energy-efficient architectures. Furthermore, we highlight the importance of precise hardware parameters measurement, showing that accurate hardware modeling is critical for obtaining CNNs with good accuracy-energy trade-offs. Our results show, that without precise hardware parameter measurement, the HW-aware NAS can produce acceptable results but may fail to fully exploit the potential of hardware accelerator, especially if the 8xN-bit approximate multipliers are considered, ultimately limiting the efficiency of designed architectures.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GA24-10990S" target="_blank" >GA24-10990S: Strojové učení zohledňující hardware: Od automatizovaného návrhu k inovativním a vysvětlitelným řešením</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2025 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

979-8-3315-2801-0

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

161-164

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Lyon

Místo konání akce

Lyon

Datum konání akce

5. 5. 2025

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001506891000029