Integrated Circuit Die Level Yield Prediction Using Deep Learning

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F03985181%3A_____%2F22%3AN0000001" target="_blank" >RIV/03985181:_____/22:N0000001 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9792526" target="_blank" >https://ieeexplore.ieee.org/document/9792526</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ASMC54647.2022.9792526" target="_blank" >10.1109/ASMC54647.2022.9792526</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Integrated Circuit Die Level Yield Prediction Using Deep Learning

Popis výsledku v původním jazyce

P. Lenhard, A. Kovalenko and R. Lenhard, "Integrated Circuit Die Level Yield Prediction Using Deep Learning," 2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2022, pp. 1-6 Abstract—Given the integrated circuits (IC) production scale, the amount of process control monitoring PCM) data enable to develop an efficient algorithm for IC yield prediction at the die-level. Therefore, in addition to cost-effective and time-efficient yield evaluation, the proposed model is able to identify failed dice and low-yield areas on a wafer without any direct electrical die testing. Additionally, for non-parametric random dice failure detection that are untraceable by PCM input based models, an ensemble learning including both PCM and die defect inspection data are described. As Wafer Sort (WS) consumes a lot of time and resources with high associated cost a significant cost reduction can be achieved using smart product routing with selective WS by employing the aforementioned die level predictive model.

Název v anglickém jazyce

Integrated Circuit Die Level Yield Prediction Using Deep Learning

Popis výsledku anglicky

P. Lenhard, A. Kovalenko and R. Lenhard, "Integrated Circuit Die Level Yield Prediction Using Deep Learning," 2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2022, pp. 1-6 Abstract—Given the integrated circuits (IC) production scale, the amount of process control monitoring PCM) data enable to develop an efficient algorithm for IC yield prediction at the die-level. Therefore, in addition to cost-effective and time-efficient yield evaluation, the proposed model is able to identify failed dice and low-yield areas on a wafer without any direct electrical die testing. Additionally, for non-parametric random dice failure detection that are untraceable by PCM input based models, an ensemble learning including both PCM and die defect inspection data are described. As Wafer Sort (WS) consumes a lot of time and resources with high associated cost a significant cost reduction can be achieved using smart product routing with selective WS by employing the aforementioned die level predictive model.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20205 - Automation and control systems

Projekt

<a href="/cs/project/FW01010089" target="_blank" >FW01010089: Výzkum a vývoj digitálních technologií pro pokročilé polovodičové procesy</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

ISBN

978-1-6654-9488-5

ISSN

2376-6697

e-ISSN

—

Počet stran výsledku

6

Strana od-do

1-6

Název nakladatele

IEEE

Místo vydání

—

Místo konání akce

Saratoga Springs, NY, USA

Datum konání akce

2. 5. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

—