Application dependent FPGA testing method using compressed deterministic test vectors

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F10%3A%230002875" target="_blank" >RIV/46747885:24220/10:#0002875 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5560208" target="_blank" >http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5560208</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/IOLTS.2010.5560208" target="_blank" >10.1109/IOLTS.2010.5560208</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Application dependent FPGA testing method using compressed deterministic test vectors

Popis výsledku v původním jazyce

Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm - compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates

Název v anglickém jazyce

Application dependent FPGA testing method using compressed deterministic test vectors

Popis výsledku anglicky

Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm - compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2010 IEEE 16th International On-Line Testing Symposium (IOLTS)

ISBN

978-1-4244-7724-1

ISSN

—

e-ISSN

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Počet stran výsledku

2

Strana od-do

192-193

Název nakladatele

IEEE

Místo vydání

Atheny

Místo konání akce

Corfu

Datum konání akce

1. 1. 2010

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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