On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F13%3A%230002862" target="_blank" >RIV/46747885:24220/13:#0002862 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84881354575" target="_blank" >http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84881354575</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2013.6549813" target="_blank" >10.1109/DDECS.2013.6549813</a>

Jazyk výsledku

angličtina

Název v původním jazyce

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

Popis výsledku v původním jazyce

This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scalesmuch better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploratio

Název v anglickém jazyce

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

Popis výsledku anglicky

This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scalesmuch better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploratio

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/LD13019" target="_blank" >LD13019: SPONA - Zvýšení spolehlivosti nanoscale obvodů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

978-1-4673-6135-4

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

181-186

Název nakladatele

IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA

Místo vydání

—

Místo konání akce

Karlovy Vary; Czech Republic

Datum konání akce

1. 1. 2013

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000325168900039