On performance estimation of a scalable VLIW soft-core on Altera and Xilinx FPGA platforms

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

On performance estimation of a scalable VLIW soft-core on Altera and Xilinx FPGA platforms

Popis výsledku v původním jazyce

This paper presents performance estimations for a scalable VLIW soft-core implemented in various XILINX and ALTERA FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families of both providers. The results present the maximal clock frequency of the complete design including the processor core and the code and data memories. In the soft-core scaling experiment, the number of available execution units is scaled from 1 to 12. In the technology scaling experiment, the core was mapped to devices of semiconductor technology nodes from 90 nm down to the latest 28nm technology. The experiments show some interesting behaviour. For example, for small-sized cores the XILINX board outperforms the ALTERA, while for larger sized cores this situation completely changes. Finally, both FPGA platforms and ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

Název v anglickém jazyce

On performance estimation of a scalable VLIW soft-core on Altera and Xilinx FPGA platforms

Popis výsledku anglicky

This paper presents performance estimations for a scalable VLIW soft-core implemented in various XILINX and ALTERA FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families of both providers. The results present the maximal clock frequency of the complete design including the processor core and the code and data memories. In the soft-core scaling experiment, the number of available execution units is scaled from 1 to 12. In the technology scaling experiment, the core was mapped to devices of semiconductor technology nodes from 90 nm down to the latest 28nm technology. The experiments show some interesting behaviour. For example, for small-sized cores the XILINX board outperforms the ALTERA, while for larger sized cores this situation completely changes. Finally, both FPGA platforms and ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/LD13019" target="_blank" >LD13019: SPONA - Zvýšení spolehlivosti nanoscale obvodů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

18th International Conference on Applied Electronics, AE 2013

ISBN

9788026101666

ISSN

1803-7232

e-ISSN

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Počet stran výsledku

4

Strana od-do

209-212

Název nakladatele

IEEE Computer Society

Místo vydání

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Místo konání akce

Pilsen; Czech Republic

Datum konání akce

1. 1. 2013

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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