Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F14%3A43921954" target="_blank" >RIV/49777513:23220/14:43921954 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6868819" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6868819</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2014.6868819" target="_blank" >10.1109/DDECS.2014.6868819</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA

Popis výsledku v původním jazyce

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed.

Název v anglickém jazyce

Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA

Popis výsledku anglicky

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

—

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

ISBN

978-1-4799-4558-0

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

318-321

Název nakladatele

IEEE (The Institute of Electrical and Electronics Engineers)

Místo vydání

Varšava

Místo konání akce

Varšava

Datum konání akce

23. 4. 2014

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000346734200069