High performance VHDL FIR filter structure for symbol timing system implemented on FPGA

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

High performance VHDL FIR filter structure for symbol timing system implemented on FPGA

Popis výsledku v původním jazyce

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. Digital filters are necessary in transmitter / receiver side and FIR filters are often chosen for their beneficial properties against IIR filters. Symbol synchronization subsystem also maintains digital filters for interpolation purpose. The goal of this paper is to develop efficient fully parallel FIR filter structure in VHDL language for symbol synchronization purpose. The first part of this paper is focused on formulation distributed arithmetic technique for proposed FIR filter. The second part describes incorporation of this filter to symbol synchronization subsystem. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size. The result of RTL synthesis on FPGA is finally discussed.

Název v anglickém jazyce

High performance VHDL FIR filter structure for symbol timing system implemented on FPGA

Popis výsledku anglicky

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. Digital filters are necessary in transmitter / receiver side and FIR filters are often chosen for their beneficial properties against IIR filters. Symbol synchronization subsystem also maintains digital filters for interpolation purpose. The goal of this paper is to develop efficient fully parallel FIR filter structure in VHDL language for symbol synchronization purpose. The first part of this paper is focused on formulation distributed arithmetic technique for proposed FIR filter. The second part describes incorporation of this filter to symbol synchronization subsystem. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size. The result of RTL synthesis on FPGA is finally discussed.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2014 22nd Telecommunications Forum (TELFOR)

ISBN

978-1-4799-6190-0

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

477-480

Název nakladatele

Telecommunications Society Belgrade, Serbia

Místo vydání

Bělěhrad

Místo konání akce

Bělehrad

Datum konání akce

25. 11. 2014

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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