A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61389005%3A_____%2F23%3A00577059" target="_blank" >RIV/61389005:_____/23:00577059 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/TNS.2023.3299333" target="_blank" >https://doi.org/10.1109/TNS.2023.3299333</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TNS.2023.3299333" target="_blank" >10.1109/TNS.2023.3299333</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

Popis výsledku v původním jazyce

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (<2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5 x 1.5 mm including a matrix of 32 x 32 pixels with a pitch of 15 mu m. The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 mu m(2) and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.

Název v anglickém jazyce

A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

Popis výsledku anglicky

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (<2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5 x 1.5 mm including a matrix of 32 x 32 pixels with a pitch of 15 mu m. The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 mu m(2) and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10304 - Nuclear physics

Projekt

<a href="/cs/project/LM2023040" target="_blank" >LM2023040: Výzkumná infrastruktura pro experimenty v CERN</a><br>

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Transactions on Nuclear Science

ISSN

0018-9499

e-ISSN

1558-1578

Svazek periodika

70

Číslo periodika v rámci svazku

9

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

10

Strana od-do

2191-2200

Kód UT WoS článku

001073607800005

EID výsledku v databázi Scopus

2-s2.0-85166291350