Field programmable gate arrays-based differential evolution coprocessor: A case study of spectrum allocation in cognitive radio network

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27240%2F13%3A86089342" target="_blank" >RIV/61989100:27240/13:86089342 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1049/iet-cdt.2012.0109" target="_blank" >http://dx.doi.org/10.1049/iet-cdt.2012.0109</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1049/iet-cdt.2012.0109" target="_blank" >10.1049/iet-cdt.2012.0109</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Field programmable gate arrays-based differential evolution coprocessor: A case study of spectrum allocation in cognitive radio network

Popis výsledku v původním jazyce

In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T Field Programmable Gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorithm is implemented in the coprocessor whereas both fixed and floating point DE are implemented in the embedded processor. Performance of the coprocessor is evaluated by optimising benchmark functions of different complexities. The implementation results show that the coprocessor is 73.14-160.2x and 2.19-27.63x faster compared to the software execution time of thefloating and fixed point algorithm respectively. As a case study, spectrum allocation problem of cognitive radio network is evaluated with the coprocessor. Results show an acceleration of 76.79-105x and 5.19-6.91x with respect to floating

Název v anglickém jazyce

Field programmable gate arrays-based differential evolution coprocessor: A case study of spectrum allocation in cognitive radio network

Popis výsledku anglicky

In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T Field Programmable Gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorithm is implemented in the coprocessor whereas both fixed and floating point DE are implemented in the embedded processor. Performance of the coprocessor is evaluated by optimising benchmark functions of different complexities. The implementation results show that the coprocessor is 73.14-160.2x and 2.19-27.63x faster compared to the software execution time of thefloating and fixed point algorithm respectively. As a case study, spectrum allocation problem of cognitive radio network is evaluated with the coprocessor. Results show an acceleration of 76.79-105x and 5.19-6.91x with respect to floating

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IET Computers and Digital Techniques

ISSN

1751-8601

e-ISSN

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Svazek periodika

7

Číslo periodika v rámci svazku

5

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

14

Strana od-do

221-334

Kód UT WoS článku

000323542800004

EID výsledku v databázi Scopus

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