FPGA Implementation of a Simple 3D Graphics Pipeline

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27240%2F15%3A86096920" target="_blank" >RIV/61989100:27240/15:86096920 - isvavai.cz</a>

Výsledek na webu

<a href="http://advances.utc.sk/index.php/AEEE/article/view/1125/1037" target="_blank" >http://advances.utc.sk/index.php/AEEE/article/view/1125/1037</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.15598/aeee.v13i1.1125" target="_blank" >10.15598/aeee.v13i1.1125</a>

Jazyk výsledku

angličtina

Název v původním jazyce

FPGA Implementation of a Simple 3D Graphics Pipeline

Popis výsledku v původním jazyce

Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGAbased implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation) and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000 fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance

Název v anglickém jazyce

FPGA Implementation of a Simple 3D Graphics Pipeline

Popis výsledku anglicky

Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGAbased implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation) and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000 fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

—

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Advances in Electrical and Electronic Engineering

ISSN

1336-1376

e-ISSN

—

Svazek periodika

13

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

9

Strana od-do

39-47

Kód UT WoS článku

—

EID výsledku v databázi Scopus

2-s2.0-84925384466