The HARPA approach to ensure dependable performance

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F18%3A10243883" target="_blank" >RIV/61989100:27740/18:10243883 - isvavai.cz</a>

Výsledek na webu

<a href="https://link.springer.com/chapter/10.1007/978-3-319-91962-1_1" target="_blank" >https://link.springer.com/chapter/10.1007/978-3-319-91962-1_1</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/978-3-319-91962-1_1" target="_blank" >10.1007/978-3-319-91962-1_1</a>

Jazyk výsledku

angličtina

Název v původním jazyce

The HARPA approach to ensure dependable performance

Popis výsledku v původním jazyce

The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors. (C) Springer International Publishing AG, part of Springer Nature 2019.

Název v anglickém jazyce

The HARPA approach to ensure dependable performance

Popis výsledku anglicky

The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors. (C) Springer International Publishing AG, part of Springer Nature 2019.

Druh

C - Kapitola v odborné knize

CEP obor

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OECD FORD obor

10200 - Computer and information sciences

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název knihy nebo sborníku

Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach

ISBN

978-3-319-91961-4

Počet stran výsledku

19

Strana od-do

1-19

Počet stran knihy

325

Název nakladatele

Springer

Místo vydání

Cham

Kód UT WoS kapitoly

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