HARPA: Tackling Physically Induced Performance Variability

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F17%3A10237290" target="_blank" >RIV/61989100:27740/17:10237290 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/7926965/" target="_blank" >http://ieeexplore.ieee.org/document/7926965/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.23919/DATE.2017.7926965" target="_blank" >10.23919/DATE.2017.7926965</a>

Jazyk výsledku

angličtina

Název v původním jazyce

HARPA: Tackling Physically Induced Performance Variability

Popis výsledku v původním jazyce

Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an everlasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and non-negligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance).

Název v anglickém jazyce

HARPA: Tackling Physically Induced Performance Variability

Popis výsledku anglicky

Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an everlasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and non-negligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance).

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

V - Vyzkumna aktivita podporovana z jinych verejnych zdroju

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2017 Design Automation and Test in Europe Conference and Exhibition

ISBN

978-3-9815370-9-3

ISSN

1530-1591

e-ISSN

1558-1101

Počet stran výsledku

6

Strana od-do

97-102

Název nakladatele

IEEE

Místo vydání

Vienna

Místo konání akce

EPFL Campus, Lausanne

Datum konání akce

27. 3. 2017

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

000404171500017