Memory Optimization for Packet Classification Algorithms in FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F10%3A00006835" target="_blank" >RIV/63839172:_____/10:00006835 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26230/10:PU89522

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Memory Optimization for Packet Classification Algorithms in FPGA

Popis výsledku v původním jazyce

Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.

Název v anglickém jazyce

Memory Optimization for Packet Classification Algorithms in FPGA

Popis výsledku anglicky

Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

978-1-4244-6610-8

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

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Název nakladatele

IEEE Computer Society

Místo vydání

Vídeň

Místo konání akce

Vídeň

Datum konání akce

1. 1. 2010

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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