Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133008" target="_blank" >RIV/63839172:_____/18:10133008 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26230/18:PU127443

Výsledek na webu

<a href="http://dx.doi.org/10.1145/3174243.3174250" target="_blank" >http://dx.doi.org/10.1145/3174243.3174250</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3174243.3174250" target="_blank" >10.1145/3174243.3174250</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Popis výsledku v původním jazyce

As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.

Název v anglickém jazyce

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Popis výsledku anglicky

As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20202 - Communication engineering and systems

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

ISBN

978-1-4503-5614-5

ISSN

—

e-ISSN

neuvedeno

Počet stran výsledku

10

Strana od-do

—

Název nakladatele

ACM

Místo vydání

New York, NY, USA

Místo konání akce

Monterey, CALIFORNIA, USA

Datum konání akce

25. 2. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

—