Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F20%3A10133291" target="_blank" >RIV/63839172:_____/20:10133291 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26230/20:PU138631

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00020" target="_blank" >http://dx.doi.org/10.1109/DSD51259.2020.00020</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00020" target="_blank" >10.1109/DSD51259.2020.00020</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs

Popis výsledku v původním jazyce

As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses.The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400 Gbps, 1 Tbps and even 2 Tbps Ethernet links.

Název v anglickém jazyce

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs

Popis výsledku anglicky

As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses.The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400 Gbps, 1 Tbps and even 2 Tbps Ethernet links.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 23rd Euromicro Conference on Digital Systems Design (DSD)

ISBN

978-1-72819-535-3

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

49-56

Název nakladatele

IEEE Computer Society

Místo vydání

Neuveden

Místo konání akce

Kranj, Slovenia

Datum konání akce

26. 8. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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