DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F21%3A10133351" target="_blank" >RIV/63839172:_____/21:10133351 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/FCCM51124.2021.00045" target="_blank" >http://dx.doi.org/10.1109/FCCM51124.2021.00045</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/FCCM51124.2021.00045" target="_blank" >10.1109/FCCM51124.2021.00045</a>

Jazyk výsledku

angličtina

Název v původním jazyce

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers

Popis výsledku v původním jazyce

FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G Ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of 400Gbps. Currently available architectures are limited to throughput up to 100Gbps and are therefore not suitable for this use case.This paper presents a vendor-independent DMA architecture that is capable of scaling up to 400Gbps throughput in a single FPGA using two PCIe Gen4 x16 slots bifurcated into four x8 interfaces. This architecture is designed to support hundreds of independent DMA channels and supports one or more PCIe endpoints with different configurations. We also demonstrate the performance of the proposed DMA architecture using results measured on an accelerator card with Intel Stratix 10 DX FPGA.

Název v anglickém jazyce

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers

Popis výsledku anglicky

FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G Ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of 400Gbps. Currently available architectures are limited to throughput up to 100Gbps and are therefore not suitable for this use case.This paper presents a vendor-independent DMA architecture that is capable of scaling up to 400Gbps throughput in a single FPGA using two PCIe Gen4 x16 slots bifurcated into four x8 interfaces. This architecture is designed to support hundreds of independent DMA channels and supports one or more PCIe endpoints with different configurations. We also demonstrate the performance of the proposed DMA architecture using results measured on an accelerator card with Intel Stratix 10 DX FPGA.

Druh

O - Ostatní výsledky

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/LM2018140" target="_blank" >LM2018140: e-Infrastruktura CZ</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů