Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F24%3A10133689" target="_blank" >RIV/63839172:_____/24:10133689 - isvavai.cz</a>

Výsledek na webu

<a href="https://dpdksummitapac24.sched.com/event/1eebU/monitoring-400g-traffic-in-dpdk-using-fpga-based-smartnic-with-rte-flow-david-vodak-cesnet" target="_blank" >https://dpdksummitapac24.sched.com/event/1eebU/monitoring-400g-traffic-in-dpdk-using-fpga-based-smartnic-with-rte-flow-david-vodak-cesnet</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow

Popis výsledku v původním jazyce

As 400G wire speed becomes more widely adopted, the need to monitor traffic at 400G is growing daily. DPDK can be a great help to achieve this speed as it provides excellent throughput results. However, monitoring packets at 400G can be challenging, so hardware acceleration also comes in handy. FPGA chips are a suitable option because they can be programmed to perform hardware offload and are powerful enough to support the processing pipeline even at 400G. Developers at CESNET have designed the first 400G FPGA-based SmartNIC that supports DPDK. It contains the Intel Agilex 7 FPGA, which provides enough resources to implement a processing pipeline. This pipeline is able to mark and filter packets and much more at 400 Gbps. It can be configured via RTE flow to help accelerate monitoring as well as many other tasks.

Název v anglickém jazyce

Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow

Popis výsledku anglicky

As 400G wire speed becomes more widely adopted, the need to monitor traffic at 400G is growing daily. DPDK can be a great help to achieve this speed as it provides excellent throughput results. However, monitoring packets at 400G can be challenging, so hardware acceleration also comes in handy. FPGA chips are a suitable option because they can be programmed to perform hardware offload and are powerful enough to support the processing pipeline even at 400G. Developers at CESNET have designed the first 400G FPGA-based SmartNIC that supports DPDK. It contains the Intel Agilex 7 FPGA, which provides enough resources to implement a processing pipeline. This pipeline is able to mark and filter packets and much more at 400 Gbps. It can be configured via RTE flow to help accelerate monitoring as well as many other tasks.

Druh

A - Audiovizuální tvorba

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/VJ02010024" target="_blank" >VJ02010024: Analýza šifrovaného provozu pomocí síťových toků</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

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Název nakladatele resp. objednatele

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