Rozvrhování iterativních algoritmů s maticovými operacemi pro efektivní FPGA návrh - Implementace Finite interval Constant Modulus algoritmu

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F07%3A00075925" target="_blank" >RIV/67985556:_____/07:00075925 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21230/07:00129445

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design?Implementation of Finite Interval Constant Modulus Algorithm

Popis výsledku v původním jazyce

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in FPGA, using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the FI-CMA. Two arithmetic libraries were used in the FPGA implementation: one based on the logarithmic number system, the other using floating-point number system in the IEEE format. Both libraries use pipelined modules. Traditional approaches to the scheduling of nested loopslead to a relatively large code, which is unsuitable for FPGA design. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, an important part of the article is devoted to the reduction of the problem size.

Název v anglickém jazyce

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design?Implementation of Finite Interval Constant Modulus Algorithm

Popis výsledku anglicky

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in FPGA, using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the FI-CMA. Two arithmetic libraries were used in the FPGA implementation: one based on the logarithmic number system, the other using floating-point number system in the IEEE format. Both libraries use pipelined modules. Traditional approaches to the scheduling of nested loopslead to a relatively large code, which is unsuitable for FPGA design. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, an important part of the article is devoted to the reduction of the problem size.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

BA - Obecná matematika

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2007

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology

ISSN

0922-5773

e-ISSN

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Svazek periodika

46

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

19

Strana od-do

35-53

Kód UT WoS článku

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EID výsledku v databázi Scopus

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