UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F13%3A00380863" target="_blank" >RIV/67985556:_____/13:00380863 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1007/978-1-4614-2410-9" target="_blank" >http://dx.doi.org/10.1007/978-1-4614-2410-9</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/978-1-4614-2410-9" target="_blank" >10.1007/978-1-4614-2410-9</a>

Jazyk výsledku

angličtina

Název v původním jazyce

UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

Popis výsledku v původním jazyce

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binarycompatibility with existing legacy programs. * Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; * Provides VHDL sources for the described processor; * Describes a latency-tolerant framework for couplinghardware accelerators to microthreaded processor pipelines; * Includes programming by example in the micro-threaded assembly language.

Název v anglickém jazyce

UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

Popis výsledku anglicky

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binarycompatibility with existing legacy programs. * Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; * Provides VHDL sources for the described processor; * Describes a latency-tolerant framework for couplinghardware accelerators to microthreaded processor pipelines; * Includes programming by example in the micro-threaded assembly language.

Druh

B - Odborná kniha

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/7E08013" target="_blank" >7E08013: Architecture Paradigms and Programming Languages for Efficient programming of multiple COREs</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

978-1-4614-2409-3

Počet stran knihy

209

Název nakladatele

Springer

Místo vydání

New York

Kód UT WoS knihy

—