An Accelerator for Kohonen Self-Organizing Maps

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00126094" target="_blank" >RIV/68407700:21230/06:00126094 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

An Accelerator for Kohonen Self-Organizing Maps

Popis výsledku v původním jazyce

In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors intotwo dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification.Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL.

Název v anglickém jazyce

An Accelerator for Kohonen Self-Organizing Maps

Popis výsledku anglicky

In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors intotwo dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification.Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2006

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Digital Technologies 2006 - 3rd International Workshop

ISBN

80-8070-637-9

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

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Název nakladatele

Žilinská universita, Elektrotechnická fakulta

Místo vydání

Žilina

Místo konání akce

Žilina

Datum konání akce

1. 12. 2006

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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