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Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03120621" target="_blank" >RIV/68407700:21230/06:03120621 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

A concept of accelerator for Kohonen Self-Organizing Maps

Popis výsledku v původním jazyce

In his work we are describing possibilities of Kohonen Self-Organizing Map hardware implementation. The essential feature of that kind of ANN is that they have ability to visualize data. We use this feature for facilitating neurologist diagnosis and prognosis. Our motivation was to find a modification suitable for hardware implementation of KSOM algorithm in order to use it efficiently during speech signal processing. Our neurocomputer is being realized on FPGA. We decided to use distributed architecture with elementary computing units connected to a specific data path topology. Architecture itself allows scalability and modifications. These features give us ability to accommodate neurocomputer with extra peripherals suitable for specific tasks and customize neurocomputer to a particular demands of specific data processing tasks. VHDL has been selected for the hardware description, so it can be easily modified and simulated on PC with free available development tools for VHDL.

Název v anglickém jazyce

A concept of accelerator for Kohonen Self-Organizing Maps

Popis výsledku anglicky

In his work we are describing possibilities of Kohonen Self-Organizing Map hardware implementation. The essential feature of that kind of ANN is that they have ability to visualize data. We use this feature for facilitating neurologist diagnosis and prognosis. Our motivation was to find a modification suitable for hardware implementation of KSOM algorithm in order to use it efficiently during speech signal processing. Our neurocomputer is being realized on FPGA. We decided to use distributed architecture with elementary computing units connected to a specific data path topology. Architecture itself allows scalability and modifications. These features give us ability to accommodate neurocomputer with extra peripherals suitable for specific tasks and customize neurocomputer to a particular demands of specific data processing tasks. VHDL has been selected for the hardware description, so it can be easily modified and simulated on PC with free available development tools for VHDL.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2006

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings EDS'06 IMAPS CS International Conference

ISBN

80-214-3246-2

ISSN

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e-ISSN

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Počet stran výsledku

5

Strana od-do

1-5

Název nakladatele

VUT v Brně, FEKT

Místo vydání

Brno

Místo konání akce

Brno

Datum konání akce

14. 9. 2006

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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