Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00375910" target="_blank" >RIV/68407700:21240/24:00375910 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/MECO62516.2024.10577851" target="_blank" >https://doi.org/10.1109/MECO62516.2024.10577851</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/MECO62516.2024.10577851" target="_blank" >10.1109/MECO62516.2024.10577851</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA

Popis výsledku v původním jazyce

This paper is focused on neural network implementation on FPGA. Linearly approximated functions combined with quantization are used to efficiently implement neural networks in hardware. Famous benchmarks were used for learning, evaluation, and hardware testing. Approximation-aware and quantization-aware learning were used to obtain weights for neurons in hardware. We implemented a neural network with an 8-bit architecture in VHDL and synthesized it to Zynq FPGA in Vivado. The resulting design running at 100MHz clock frequency was carefully tested against hardware-accurate models written in Wolfram Mathematica and C++. We present a decrease in FPGA resources and chip utilization compared to 16-bit architecture implementation.

Název v anglickém jazyce

Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA

Popis výsledku anglicky

This paper is focused on neural network implementation on FPGA. Linearly approximated functions combined with quantization are used to efficiently implement neural networks in hardware. Famous benchmarks were used for learning, evaluation, and hardware testing. Approximation-aware and quantization-aware learning were used to obtain weights for neurons in hardware. We implemented a neural network with an 8-bit architecture in VHDL and synthesized it to Zynq FPGA in Vivado. The resulting design running at 100MHz clock frequency was carefully tested against hardware-accurate models written in Wolfram Mathematica and C++. We present a decrease in FPGA resources and chip utilization compared to 16-bit architecture implementation.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2024 13th Mediterranean Conference on Embedded Computing (MECO)

ISBN

979-8-3503-8756-8

ISSN

2377-5475

e-ISSN

2637-9511

Počet stran výsledku

4

Strana od-do

98-101

Název nakladatele

Institute of Electrical and Electronic Engineers

Místo vydání

Piscataway

Místo konání akce

Budva

Datum konání akce

11. 6. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001268606200050