Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00366854" target="_blank" >RIV/68407700:21240/23:00366854 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/MECO58584.2023.10155065" target="_blank" >https://doi.org/10.1109/MECO58584.2023.10155065</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/MECO58584.2023.10155065" target="_blank" >10.1109/MECO58584.2023.10155065</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

Popis výsledku v původním jazyce

Integrating artificial intelligence technologies into embedded systems requires efficient implementation of neural networks in hardware. The paper presents a Zynq 7020 FPGA implementation and evaluation of a middle-sized dense neural network based on approximate computation by linearly approximated functions. Three famous benchmarks were used for classification accuracy evaluation and hardware testing. We use our highly pipelined neural hardware architecture that takes weights from block RAMs to save logic resources and enables their update from the processing system. The architecture reaches excellent design scalability, allowing us to estimate the number of neurons implemented in programmable logic based on single-neuron resources. We reached nearly full chip utilization while preserving the high clock frequency for the FPGA used.

Název v anglickém jazyce

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

Popis výsledku anglicky

Integrating artificial intelligence technologies into embedded systems requires efficient implementation of neural networks in hardware. The paper presents a Zynq 7020 FPGA implementation and evaluation of a middle-sized dense neural network based on approximate computation by linearly approximated functions. Three famous benchmarks were used for classification accuracy evaluation and hardware testing. We use our highly pipelined neural hardware architecture that takes weights from block RAMs to save logic resources and enables their update from the processing system. The architecture reaches excellent design scalability, allowing us to estimate the number of neurons implemented in programmable logic based on single-neuron resources. We reached nearly full chip utilization while preserving the high clock frequency for the FPGA used.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 2023 12th Mediterranean Conference on Embedded Computing (MECO)

ISBN

979-8-3503-2291-0

ISSN

2637-9511

e-ISSN

2637-9511

Počet stran výsledku

4

Strana od-do

1-4

Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Budva

Datum konání akce

6. 6. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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