Approximate arithmetic for modern neural networks and FPGAs

Kód výsledku v IS VaVaI

RIV/68407700:21240/22:00358459 - isvavai.cz

Výsledek na webu

https://doi.org/10.1109/MECO55406.2022.9797141

DOI - Digital Object Identifier

10.1109/MECO55406.2022.9797141

Jazyk výsledku

angličtina

Název v původním jazyce

Approximate arithmetic for modern neural networks and FPGAs

Popis výsledku v původním jazyce

Approximate arithmetic is a very important approach for implementing neural networks in embedded hardware. The requirements of real-time applications with respect to the size of deep neural networks force designers to simplify the neural processing elements. Not only the reduction of precision of model parameters to a few bits, but also the use of approximate arithmetic increases computational power and saves on-chip resources beyond exact computation. Since it was shown that linearly approximated functions are suitable for implementing neural networks in hardware, FPGAs have improved. So we decided to re-implement the processing element on a modern FPGA and to present implementation results regarding speed and resource consumption. A neural processing element based on linearly approximated functions was implemented in Vivado and tested on an xc7 FPGA. The results show that the architecture saves significant resources and a clock frequency above 100 MHz can be achieved in pipelined design.

Název v anglickém jazyce

Approximate arithmetic for modern neural networks and FPGAs

Popis výsledku anglicky

Approximate arithmetic is a very important approach for implementing neural networks in embedded hardware. The requirements of real-time applications with respect to the size of deep neural networks force designers to simplify the neural processing elements. Not only the reduction of precision of model parameters to a few bits, but also the use of approximate arithmetic increases computational power and saves on-chip resources beyond exact computation. Since it was shown that linearly approximated functions are suitable for implementing neural networks in hardware, FPGAs have improved. So we decided to re-implement the processing element on a modern FPGA and to present implementation results regarding speed and resource consumption. A neural processing element based on linearly approximated functions was implemented in Vivado and tested on an xc7 FPGA. The results show that the architecture saves significant resources and a clock frequency above 100 MHz can be achieved in pipelined design.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 11th Mediterranean Conference on Embedded Computing (MECO 2022)

ISBN

978-1-6654-6828-2

ISSN

2377-5475

e-ISSN

—

Počet stran výsledku

4

Strana od-do

351-354

Název nakladatele

Institute of Electrical and Electronics Engineers, Inc.

Místo vydání

—

Místo konání akce

Budva

Datum konání akce

7. 6. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000855969800072