Many-valued memory circuits-implementation in the model of many-valued logical circuits

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Many-valued memory circuits-implementation in the model of many-valued logical circuits

Popis výsledku v původním jazyce

In this presentation, a memory circuit (flip-flop) build in the model of many-valued logical circuits is presented. The design of the memory circuit is based on finding an appropriate many-valued logical operation which replaces the Sheffer resp. Pierceoperation which is used in the R-S memory circuit known from the two-valued logical circuits. We prove that, in the ideal case, the generalized many-valued R-S memory circuit can store and hold any logical value from the real interval [0,1] in a similarway as the two valued R-S memory circuit. The proposed many-valued R-S memory circuit allows moreover to design a many-valued level-controlled memory circuit and a many-valued edge-controlled memory circuit. Problems of the stability of the memory circuit with respect to small errors of input signals and to small errors of the gates are discussed. It is shown that unstability of the gates may violate the proper functionality of the circuit. Nevertheless, the problem can be solved by rest

Název v anglickém jazyce

Many-valued memory circuits-implementation in the model of many-valued logical circuits

Popis výsledku anglicky

In this presentation, a memory circuit (flip-flop) build in the model of many-valued logical circuits is presented. The design of the memory circuit is based on finding an appropriate many-valued logical operation which replaces the Sheffer resp. Pierceoperation which is used in the R-S memory circuit known from the two-valued logical circuits. We prove that, in the ideal case, the generalized many-valued R-S memory circuit can store and hold any logical value from the real interval [0,1] in a similarway as the two valued R-S memory circuit. The proposed many-valued R-S memory circuit allows moreover to design a many-valued level-controlled memory circuit and a many-valued edge-controlled memory circuit. Problems of the stability of the memory circuit with respect to small errors of input signals and to small errors of the gates are discussed. It is shown that unstability of the gates may violate the proper functionality of the circuit. Nevertheless, the problem can be solved by rest

Druh

D - Stať ve sborníku

CEP obor

JD - Využití počítačů, robotika a její aplikace

OECD FORD obor

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Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2007

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

MEMICS proceedings 2007

ISBN

978-80-7355-077-6

ISSN

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e-ISSN

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Počet stran výsledku

1

Strana od-do

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Název nakladatele

Masarykova univerzita

Místo vydání

Brno

Místo konání akce

Znojmo

Datum konání akce

26. 10. 2007

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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