Digital Compensation Unit for Impedance Metrology Working up to 2 MHz

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F11%3A00182420" target="_blank" >RIV/68407700:21230/11:00182420 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/IDAACS.2011.6072709" target="_blank" >http://dx.doi.org/10.1109/IDAACS.2011.6072709</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/IDAACS.2011.6072709" target="_blank" >10.1109/IDAACS.2011.6072709</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Digital Compensation Unit for Impedance Metrology Working up to 2 MHz

Popis výsledku v původním jazyce

This paper describes a design of two-channel digital compensation unit which has been developed for accuracy measurement of four-terminal-pair (4TP) impedance standards by the three-voltmeter method. The FPGA based compensation unit senses a residual voltage on the low potential port of the compared impedances continuously. The sensing process is made by means of a synchronous detection technique; a principle of the lock-in amplifiers is implemented on the FPGA. Simultaneously a voltage proportional tothe residual voltage is injected into a main measuring circuit via an injection transformer. Thanks to this feedback, residual voltages at low potential port of measured impedances are reduced more than 1000 times. A typical level of residual voltages isabout 5 uV. The compensation unit operates in the frequency range from 10 kHz up to 2 MHz. The unit is controlled by a PC via optical insulated USB port.

Název v anglickém jazyce

Digital Compensation Unit for Impedance Metrology Working up to 2 MHz

Popis výsledku anglicky

This paper describes a design of two-channel digital compensation unit which has been developed for accuracy measurement of four-terminal-pair (4TP) impedance standards by the three-voltmeter method. The FPGA based compensation unit senses a residual voltage on the low potential port of the compared impedances continuously. The sensing process is made by means of a synchronous detection technique; a principle of the lock-in amplifiers is implemented on the FPGA. Simultaneously a voltage proportional tothe residual voltage is injected into a main measuring circuit via an injection transformer. Thanks to this feedback, residual voltages at low potential port of measured impedances are reduced more than 1000 times. A typical level of residual voltages isabout 5 uV. The compensation unit operates in the frequency range from 10 kHz up to 2 MHz. The unit is controlled by a PC via optical insulated USB port.

Druh

D - Stať ve sborníku

CEP obor

JB - Senzory, čidla, měření a regulace

OECD FORD obor

—

Projekt

—

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Intelligent Data Acquisition and Advanced Computing Systems (IDAACS)

ISBN

978-1-4577-1423-8

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

50-53

Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Prague

Datum konání akce

15. 9. 2011

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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