Structure, Modeling and Realization of True Random Number Generator with Analog Noise Amplification

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Structure, Modeling and Realization of True Random Number Generator with Analog Noise Amplification

Popis výsledku v původním jazyce

This paper deals with true random number generator (TRNG) with analog noise amplification. It is device with non-deterministic features that has to be able to generate random bits. Random number generators help to ensure the security of cryptographic andcommunication systems by the generation of different session keys or are also used in simulators of various problems, for example, in the simulators of electrical circuits. Generated sequences of random numbers have specific features such as uniform distribution and high entropy. Part of this paper is description of realized hardware generator and its software model. Base on the general architecture of TRNG, structure of this generator was proposed. For debugging of proposed structure, software model in Verilog-A HDL language was created. The hardware generator was realized on the printed circuit board. Quality of output random bit sequences from software model and from realized generator was tested by the FIPS and NIST test suites.

Název v anglickém jazyce

Structure, Modeling and Realization of True Random Number Generator with Analog Noise Amplification

Popis výsledku anglicky

This paper deals with true random number generator (TRNG) with analog noise amplification. It is device with non-deterministic features that has to be able to generate random bits. Random number generators help to ensure the security of cryptographic andcommunication systems by the generation of different session keys or are also used in simulators of various problems, for example, in the simulators of electrical circuits. Generated sequences of random numbers have specific features such as uniform distribution and high entropy. Part of this paper is description of realized hardware generator and its software model. Base on the general architecture of TRNG, structure of this generator was proposed. For debugging of proposed structure, software model in Verilog-A HDL language was created. The hardware generator was realized on the printed circuit board. Quality of output random bit sequences from software model and from realized generator was tested by the FIPS and NIST test suites.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2012

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of Electronic Devices and Systems EDS 2012

ISBN

978-80-214-4539-0

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

145-150

Název nakladatele

VUT v Brně, FEKT

Místo vydání

Brno

Místo konání akce

Brno

Datum konání akce

28. 6. 2012

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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