Behavioral Models of True Random Number Generators

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F18%3A00321795" target="_blank" >RIV/68407700:21230/18:00321795 - isvavai.cz</a>

Výsledek na webu

<a href="http://radio.feld.cvut.cz/conf/poster/proceedings/Poster_2018/Section_EI/EI_061_Kote.pdf" target="_blank" >http://radio.feld.cvut.cz/conf/poster/proceedings/Poster_2018/Section_EI/EI_061_Kote.pdf</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Behavioral Models of True Random Number Generators

Popis výsledku v původním jazyce

The behavioral models of true random number generators (TRNGs), presented in this paper, are developed to be able to approximate properties of real TRNGs and speed up system simulations on a chip containing this type of generators. The models of the TRNG with direct amplification of noise, the TRNG with ring oscillators, and TRNG based on metastable states are based on commonly used architectures. For their creation, the hardware description language Verilog-A has been used. The random number sequences have been tested by the well-known statistical test suites FIPS and NIST. According to obtained results, the introduced models substitute a function of real TRNGs very well. Using these models instead of a transistor level, the simulation time is shortened by at least ten times.

Název v anglickém jazyce

Behavioral Models of True Random Number Generators

Popis výsledku anglicky

The behavioral models of true random number generators (TRNGs), presented in this paper, are developed to be able to approximate properties of real TRNGs and speed up system simulations on a chip containing this type of generators. The models of the TRNG with direct amplification of noise, the TRNG with ring oscillators, and TRNG based on metastable states are based on commonly used architectures. For their creation, the hardware description language Verilog-A has been used. The random number sequences have been tested by the well-known statistical test suites FIPS and NIST. According to obtained results, the introduced models substitute a function of real TRNGs very well. Using these models instead of a transistor level, the simulation time is shortened by at least ten times.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the International Student Scientific Conference Poster – 22/2018

ISBN

978-80-01-06428-3

ISSN

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e-ISSN

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Počet stran výsledku

67

Strana od-do

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Název nakladatele

Czech Technical University in Prague

Místo vydání

Praha

Místo konání akce

Praha

Datum konání akce

10. 5. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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