Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00233103" target="_blank" >RIV/68407700:21230/16:00233103 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/TC.2015.2458859" target="_blank" >http://dx.doi.org/10.1109/TC.2015.2458859</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TC.2015.2458859" target="_blank" >10.1109/TC.2015.2458859</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling

Popis výsledku v původním jazyce

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

Název v anglickém jazyce

Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling

Popis výsledku anglicky

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/EE2.3.30.0034" target="_blank" >EE2.3.30.0034: Podpora zkvalitnění týmů výzkumu a vývoje a rozvoj intersektorální mobility na ČVUT v Praze</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Transactions on Computers

ISSN

0018-9340

e-ISSN

—

Svazek periodika

65

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

14

Strana od-do

1882-1895

Kód UT WoS článku

000376879300016

EID výsledku v databázi Scopus

2-s2.0-84969821600