Improvements in the Electrical Performance of IC MOSFET Components Using Diamond Layout Style Versus Traditional Rectangular Layout Style Calculated by Conformal Mapping

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00333185" target="_blank" >RIV/68407700:21230/19:00333185 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/TED.2019.2931090" target="_blank" >https://doi.org/10.1109/TED.2019.2931090</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TED.2019.2931090" target="_blank" >10.1109/TED.2019.2931090</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Improvements in the Electrical Performance of IC MOSFET Components Using Diamond Layout Style Versus Traditional Rectangular Layout Style Calculated by Conformal Mapping

Popis výsledku v původním jazyce

In the first part of this article, we have proposed an innovative approach to improve the drain current model of the MOSFETs implemented with the diamond layout style (DLS), regarding the longitudinal corner effect (LCE). The proposed model is more accurate than a previous model compared to 3-D TechnologyComputer-AidedDesign (3-D TCAD) simulation results. The new model has an innovative analytical description based on a conformal mapping theory. As a conformal mapping, there has been chosen a Schwarz–Christoffel transformation (SC). The maximal deviation values of the aspect ratio calculated by LCE are in the range from -27% to +38%. In counterpart with the new SC analytical description of DLS, the maximal deviation values are in the range from 0% to -5.5%. The second part of this article describes improvements in the electrical performance of the N-MOSFET components by using DLS counterpart to traditional rectangular layout style (RLS). Both layout style DLS, RLS, respectively, have the same process settings, as well as they are keeping the same gate area A, and an aspect ratio width to length W/L to preserve the same input conditions for their analysis. The maximal drain current increasing for the simulated DLS MOS transistor is over 20% for effective aspect ratio (W/L)eff equal to 2.0 and the angle is set to 60 grads. The presented model has a very good analytic description with the error level lower than 3%.

Název v anglickém jazyce

Improvements in the Electrical Performance of IC MOSFET Components Using Diamond Layout Style Versus Traditional Rectangular Layout Style Calculated by Conformal Mapping

Popis výsledku anglicky

In the first part of this article, we have proposed an innovative approach to improve the drain current model of the MOSFETs implemented with the diamond layout style (DLS), regarding the longitudinal corner effect (LCE). The proposed model is more accurate than a previous model compared to 3-D TechnologyComputer-AidedDesign (3-D TCAD) simulation results. The new model has an innovative analytical description based on a conformal mapping theory. As a conformal mapping, there has been chosen a Schwarz–Christoffel transformation (SC). The maximal deviation values of the aspect ratio calculated by LCE are in the range from -27% to +38%. In counterpart with the new SC analytical description of DLS, the maximal deviation values are in the range from 0% to -5.5%. The second part of this article describes improvements in the electrical performance of the N-MOSFET components by using DLS counterpart to traditional rectangular layout style (RLS). Both layout style DLS, RLS, respectively, have the same process settings, as well as they are keeping the same gate area A, and an aspect ratio width to length W/L to preserve the same input conditions for their analysis. The maximal drain current increasing for the simulated DLS MOS transistor is over 20% for effective aspect ratio (W/L)eff equal to 2.0 and the angle is set to 60 grads. The presented model has a very good analytic description with the error level lower than 3%.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Transactions on Electron Devices

ISSN

0018-9383

e-ISSN

1557-9646

Svazek periodika

66

Číslo periodika v rámci svazku

9

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

8

Strana od-do

3718-3725

Kód UT WoS článku

000482583200003

EID výsledku v databázi Scopus

2-s2.0-85071224840