Reconfiguration Based Fault Tolerant Systems Design - Survey of Approaches

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00171371" target="_blank" >RIV/68407700:21240/10:00171371 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Reconfiguration Based Fault Tolerant Systems Design - Survey of Approaches

Popis výsledku v původním jazyce

Dependability and reliability of FPGAs is today's most discussed problem while talking about their usage in critical mission application. The biggest advantage of the FPGAs is significantly lower time and cost needed to develop prototypes compared to ASICs. This is mostly achieved due to FPGA ability to change programmed function in range of tens of microseconds. That is the time required to perform partial reconfiguration or to download completely new bitstream into FPGA. Reconfiguration is the most often discussed while we talking about FPGA and Fault-Tolerant design. It's the most powerful option we have to create fault-tolerant design in FPGA, but on the other hand it also brings out a lot of problems. Design using partial reconfiguration is more complex to place and route and reconfiguration hardware itself can be source of faults. Overall the reconfiguration proposes various options to create fault-tolerant and dependable design in FPGA....

Název v anglickém jazyce

Reconfiguration Based Fault Tolerant Systems Design - Survey of Approaches

Popis výsledku anglicky

Dependability and reliability of FPGAs is today's most discussed problem while talking about their usage in critical mission application. The biggest advantage of the FPGAs is significantly lower time and cost needed to develop prototypes compared to ASICs. This is mostly achieved due to FPGA ability to change programmed function in range of tens of microseconds. That is the time required to perform partial reconfiguration or to download completely new bitstream into FPGA. Reconfiguration is the most often discussed while we talking about FPGA and Fault-Tolerant design. It's the most powerful option we have to create fault-tolerant design in FPGA, but on the other hand it also brings out a lot of problems. Design using partial reconfiguration is more complex to place and route and reconfiguration hardware itself can be source of faults. Overall the reconfiguration proposes various options to create fault-tolerant and dependable design in FPGA....

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

ISBN

978-80-87342-10-7

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

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Název nakladatele

NOVPRESS

Místo vydání

Brno

Místo konání akce

Mikulov

Datum konání akce

22. 10. 2010

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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