Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138607" target="_blank" >RIV/00216305:26230/20:PU138607 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12101/" target="_blank" >https://www.fit.vut.cz/research/publication/12101/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/VLSI-DAT49148.2020.9196269" target="_blank" >10.1109/VLSI-DAT49148.2020.9196269</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study

Popis výsledku v původním jazyce

This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a fault-tolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGAs configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent.

Název v anglickém jazyce

Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study

Popis výsledku anglicky

This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a fault-tolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGAs configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers

ISBN

978-1-7281-6083-2

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

121-124

Název nakladatele

IEEE Computer Society

Místo vydání

Hsinchu

Místo konání akce

Ambassador Hotel, Hsinchu, Taiwan

Datum konání akce

10. 8. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000612045400011