Fault-tolerant and fail-safe design based on reconfiguration

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F11%3A00179457" target="_blank" >RIV/68407700:21240/11:00179457 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.igi-global.com/embeddedcontent.aspx?PageCode=WGSLd" target="_blank" >http://www.igi-global.com/embeddedcontent.aspx?PageCode=WGSLd</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.4018/978-1-60960-212-3" target="_blank" >10.4018/978-1-60960-212-3</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Fault-tolerant and fail-safe design based on reconfiguration

Popis výsledku v původním jazyce

The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable dueto high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology.

Název v anglickém jazyce

Fault-tolerant and fail-safe design based on reconfiguration

Popis výsledku anglicky

The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable dueto high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology.

Druh

C - Kapitola v odborné knize

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název knihy nebo sborníku

Design and Test Technology for Dependable Systems-on-Chip

ISBN

978-1-60960-212-3

Počet stran výsledku

20

Strana od-do

175-194

Počet stran knihy

314

Název nakladatele

IGI Global

Místo vydání

Hershey, Pennsylvania

Kód UT WoS kapitoly

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