Dual-Rail Asynchronous Logic Multi-Level Implementation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00207600" target="_blank" >RIV/68407700:21240/14:00207600 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1016/j.vlsi.2013.02.002" target="_blank" >http://dx.doi.org/10.1016/j.vlsi.2013.02.002</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.vlsi.2013.02.002" target="_blank" >10.1016/j.vlsi.2013.02.002</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Dual-Rail Asynchronous Logic Multi-Level Implementation

Popis výsledku v původním jazyce

A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean networkof complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes aredesigned based on DIMS, direct logic, NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection log

Název v anglickém jazyce

Dual-Rail Asynchronous Logic Multi-Level Implementation

Popis výsledku anglicky

A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean networkof complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes aredesigned based on DIMS, direct logic, NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection log

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Integration, the VLSI Journal

ISSN

0167-9260

e-ISSN

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Svazek periodika

47

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

12

Strana od-do

148-159

Kód UT WoS článku

000328431900016

EID výsledku v databázi Scopus

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