Application specific processor with high level synthesized instructions

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00226369" target="_blank" >RIV/68407700:21240/14:00226369 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1145/2554688.2554754" target="_blank" >http://dx.doi.org/10.1145/2554688.2554754</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/2554688.2554754" target="_blank" >10.1145/2554688.2554754</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Application specific processor with high level synthesized instructions

Popis výsledku v původním jazyce

The paper deals with the design of application-specific processor which uses high level synthesized instruction engines. This approach is demonstrated on the instance of high speed network flow measurement processor for FPGA. Our newly proposed concept called Software Defined Monitoring (SDM) relies on advanced monitoring tasks implemented in the software supported by a configurable hardware accelerator. The monitoring tasks reside in the software and can easily control the level of detail retained by the hardware for each flow. This way, the measurement of bulk/uninteresting traffic is offloaded to the hardware, while the interesting traffic is processed in the software. SDM enables creation of flexible monitoring systems capable of deep packet inspection at high throughput. We introduce the processor architecture and a workflow that allows to create hardware accelerated measurement modules (instructions) from the description in C/C++ language. The processor offloads various aggregati

Název v anglickém jazyce

Application specific processor with high level synthesized instructions

Popis výsledku anglicky

The paper deals with the design of application-specific processor which uses high level synthesized instruction engines. This approach is demonstrated on the instance of high speed network flow measurement processor for FPGA. Our newly proposed concept called Software Defined Monitoring (SDM) relies on advanced monitoring tasks implemented in the software supported by a configurable hardware accelerator. The monitoring tasks reside in the software and can easily control the level of detail retained by the hardware for each flow. This way, the measurement of bulk/uninteresting traffic is offloaded to the hardware, while the interesting traffic is processed in the software. SDM enables creation of flexible monitoring systems capable of deep packet inspection at high throughput. We introduce the processor architecture and a workflow that allows to create hardware accelerated measurement modules (instructions) from the description in C/C++ language. The processor offloads various aggregati

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

FPGA '14 Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

ISBN

978-1-4503-2671-1

ISSN

—

e-ISSN

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Počet stran výsledku

1

Strana od-do

246

Název nakladatele

ACM

Místo vydání

New York

Místo konání akce

Monterey, CA

Datum konání akce

26. 2. 2014

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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